Threshold voltage for n-FET and p-FET

The threshold voltage (Ut) of a Field Effect Transistor (FET) is the voltage applied on the gate of the transistor at which a measurable current between source (S) and drain (D) is starting to flow. At this voltage an inversion layer under the gate (between source and drain) is formed, so that the pn-junctions (immediately under the gate) are vanishing and thus a current path between drain and source is obtained. The resistance of these this current path (inversion layer) depends on the thickness of the layer, which is determined by the applied gate voltage. A schematic overview of measurement setups for threshold voltages of N-FET and P-FET transistors is presented in Figures 1 and 2.

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